Administrative stuff
The instructor for the course this semester is Roger Chamberlain. Here is a short video about me. My office hours are immediately after class, 4-5pm on MW, in McKelvey 1053.
The text of the welcome email that I sent to the class on Fri., Aug. 21, is here.
The teaching assistant this semester is Tyler Martin. His office hours are Fri., 9-10am, in McKelvey 1037.
Class lectures are from 2:30pm to 4pm (technically 3:50pm) on Mondays and Wednesdays.
We will primarily use Piazza for communication in the class. Please use Piazza over email for asking questions. The link for the class is here. You might need to register with an @wustl.edu address your first time there.
We will use Canvas for submitting assignments and for recording/viewing of grades. The link for the class is here.
Calendar (subject to change)
- Aug 24 Introduction
Lecture slides (sorry, the recording has no audio) - Aug 26 Instruction Set Architecture (ISA)
Lecture slides - Aug 31 Instruction Set Architecture (ISA)
Lecture slides - Sep 2 Performance
Lecture slides - Sep 7 Labor Day (no class)
- Sep 9 Performance Modeling
Lecture slides - Sep 14 Pipelining
Lecture slides - Sep 16 Branch Prediction
Lecture slides - Sep 21 Superscalar
Lecture slides - Sep 23 Static Scheduling
Lecture slides - Sep 28 Dynamic Scheduling
Lecture slides - Sep 30 Dynamic Scheduling
Lecture slides - Oct 5 Fall break (no class)
- Oct 7 Review for Exam 1
Lecture slides - Oct 12 Exam 1
- Oct 14 Technology
Lecture slides - Oct 19 Caches
Lecture slides - Oct 21 Caches
Lecture slides - Oct 26 Virtual Memory
Lecture slides - Oct 28 Multithreading
Lecture slides - Nov 2 Spectre/Meltdown
Lecture slides - Nov 4 Security
Lecture slides - Nov 9 Multicores
Lecture slides - Nov 11 Multicores
Lecture slides - Nov 16 Multicores (guest lecture)
Lecture slides - Nov 18 Multiprocessors
- Nov 23 Multiprocessors
- Nov 25 Thanksgiving break (no class)
- Nov 30 Domain-specific Architectures
- Dec 2 Review for Exam 2
- Dec 7 Exam 2
- Finals week Assignment 4(c) will be due Dec 11
Reading
The optional text for the course is Jean-Loup Baer, Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors, Cambridge University Press, 2010.
- Introduction - Baer, Section 1.1
- Performance - Baer, Sections 1.2-1.4 (except 1.3.2)
- Performance Modeling - Baer, Section 1.3.2
- gem5 documentation, including an excellent introduction to learning gem5.
- A Linux tutorial put together by Joshua Glatt.
- Gem5 tutorial video (the old one) and here (start 17 min in).
- Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood, "The gem5 simulator," SIGARCH Comput. Archit. News 39(2):1-7, August 2011. DOI=10.1145/2024716.2024718.
- Jason Lowe-Power et al., "The gem5 Simulator: Version 20.0+," arXiv:2007.03152, September 2020. DOI=10.48550/arXiv.2007.03152.
- Pipelining - Baer, Section 2.1
- Branch Prediction - Baer, Section 4.1
- Technology - Baer, Section 9.1
- Superscalar - Baer, Sections 3.1, 3.2, 3.5.1
- Static Scheduling - Baer, Sections 3.3.1-3.3.4, 7.5
- Dynamic Scheduling - Baer, Sections 5.0-5.2, 5.3.3, 5.4-5.5
- Caches - Baer, Sections 2.2, 6.1-6.3.1
- Virtual Memory - Baer, Sections 2.3, 6.1.1
- Multithreading - Baer, Section 8.1
- Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom, "Spectre Attacks: Exploiting Speculative Execution," Communications of the ACM, 63(7):93-101, July 2020, DOI=10.1145/3399742
- Nadav Amit, Fred Jacobs, and Michael Wei, "JumpSwitches: Restoring the Performance of Indirect Branches In the Era of Spectre," in Proc. of USENIX Annual Technical Conference, 2019. The conference presentation is available here.
- Dayeol Lee, David Kohlbrenner, Shweta Shinde, Krste Asanović, and Dawn Song, "Keystone: An Open Framework for Architecting TEEs," arXiv:1907.10119, 2019. DOI=10.48550/arXiv.1907.10119
- Multicores - Baer, Sections 7.0, 7.1.3, 7.2-7.4, 8.2
- Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta, and John Hennessy, "The directory-based cache coherence protocol for the DASH multiprocessor," in Proc. of 17th ACM International Symposium on Computer Architecture (ISCA), pp. 148-159, 1990, DOI=10.1145/325164.325132
- Biagio Peccerillo, Mirco Mannino, Andrea Mondelli, and Sandro Bartolini, "A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives," Journal of Systems Architecture 129:102561, 2022.
- H.T. Kung, "Why Systolic Architectures?," Computer, 15(1):37-46, January 1982, DOI=10.1109/MC.1982.1653825
- Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence," in Proc. of 18th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 87-94, 2010, DOI=10.1109/FCCM.2010.22
- Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Optimal runtime reconfiguration strategies for systolic arrays," in Proc. of IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 162-167, 2009.
- Norman P. Jouppi et al., "In-Datacenter Performance Analysis of a Tensor Processing Unit," in Proc. of IEEE International Symposium on Computer Architecture (ISCA), pp. 1-12, 2017, DOI=10.1145/3079856.3080246