Frame Delay Through ATM Switches: MIMO Latency, ANSI Contribution, T1A1.3/98-056, November 2-4, 1998.

This contribution addresses the problem of measuring frame latency in ATM switches. The frames consisting of several ATM cells may arrive with numerous gaps between cells. It is important that the gaps present in the input stream be not counted towards the switch's contribution to the frame delay. The proposed solution called "MIMO" (Message-In Message-Out) latency improves upon FILO (First-In Last-Out) latency commonly used for continuous frame technologies such as frame relay. Briefly, the MIMO latency is defined as the difference between FILO latency through the switch and that through an ideal switch. The definition and the discussion also apply to any network of switches as well.

Complete contribution in Adobe Acrobat 3.0 (102,225 bytes)

Presentation slides in Adobe Acrobat 3.0 Format (267,511 bytes, 1 slide/page)

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