Course Information:
Instructor: Dr. Viktor Gruev
Email: vgruev@cse.wustl.edu
Office: Bryan 405-D
Office Hours: Tuesday and Thursday, 4:00 - 5.30PM
Class Time: Tuesday and Thursday, 5:30 - 7.00PM, Sever Hall 102
TA: Raphael Njuguna
Email:
njugunar@seas.wustl.edu
Office: Bryan 405-B or Bryan 420
Office Hours: Tuesday and Thursday, 10:00 - 11.30AM
Course Description:
This course is an introduction to VLSI digital design. The material will focus on bottom up design of digital integrated circuits, starting from CMOS transistor properties and manufacturing technology to CMOS inverters, combinational and sequential logic designs and more complex digital blocks. Important design aspect of digital integrated circuits such as propagation delay, noise margins and power dissipation will be covered in the class, as well as design challenges in submicron technology will be addressed. The students will design combinational and sequential circuits at various levels of abstraction using state‐of‐the‐art CAD environment provided by Cadence Design Systems. The goal of the class is to design transistor level digital integrated circuits in 0.5micron technology that can be fabricated by a semiconductor foundry.
The syllabus for CSE463 and CSE563 are identical. The main difference between the two classes is in the difficulty of homework problems, midterm exam and scope of final project. Since CSE563 is a graduate level class, it will contain: an extra problem for every homework, an extra problem for the midterm exam and the scope of the final project will be larger compared to CSE463.
Course Objectives:
The course will start with an overview of the intrinsic properties of CMOS transistors and an overview of fabrication methodologies for integrated circuits. Combinational circuits will be introduced with the design of the inverter circuit. The static and dynamic properties of the inverter will be studies in detail using hand calculations and SPICE simulations. The state-of-the-art tool for designing ICs, Cadence, will be introduced and will be used to design and verify the physical layout of the inverter. Using parameters extracted from Cadence layout simulations, a Verilog model will be constructed. Other CMOS combinational and sequential digital circuits, such as NAND, NOR, SR latch, flip flop and others, will be constructed and simulated at transistor, layout and behavioral level using Cadence. The final project will include a design of a complex digital system. The entire digital IC will be simulated and the final layout of the chip will be presented. The layout of the chip can be submitted for fabrication in a 0.5micron CMOS process.
Prerequisites:
ESE 232: Introduction to Electronic Circuits
CSE 362M: Computer Architecture (recommended)
Textbook:
- CMOS Digital Integrated Circuits Analysis and Design, S. M. Kang and Y. Leblebici, 2002.
- Online Cadence Tutorial
Other References:
- Verilog HDL: A guide to digital design and synthesis, S. Palnikar, 1996.
- Basic VLSI Design, D. Pucknell and K. Eshraghian 1988.
- Fundamentals of CMOS VLSI Design, J. Uyemura, 1988
- Analysis and Design of Analog integrated Circuits, P. Gray and R. Meyer, 1994
Course Grading:
Weekly Homework: 30%
Exam1: 15%
Exam2: 15%
Project: 40%
Grading Policy:
90% or above A
80% to 89% B
65% to 79% C
45% to 64% D
44% or below F
2009 Syllabus
Dates
(week beginning) |
Topics |
Chapter |
Week 1 |
Course Introduction |
1 |
Week 2 |
MOS Transistor Theory |
2 |
Week 3 |
MOS Transistor Theory
Intro to Cadence Design |
3 |
Week 4 |
Inverter: Static Characteristics |
3 |
Week 5 |
Inverter: Static Characteristics |
5 |
Week 6 |
Inverter: Switching Characteristics
Introduction to Cadence
|
6 |
Week 7 |
Combinational Logic Circuits |
7 |
Week 8 |
Combinational Logic Circuits |
7 |
Week 9 |
Combinational Logic Circuits |
7 |
Week 10 |
Sequential Logic Circuits |
8 |
Week 11 |
Sequential Logic Circuits |
8 |
Week 12 |
Dynamic Logic Circuits |
9 |
Week 13 |
Semiconductor Memories |
9, 10 |
Week 14 |
Thanksgiving Break |
|
Week 15 |
Semiconductor Memories |
10 |
Lecture Slides
Chapter 1: Introduction (slides)
Chapter 3: MOS Transistor (slides) (handout)
Chapter 5: Inverter: DC Characteristics (slides) (handout)
Chapter 6: Inverter: Transient Characteristics (slides) (handout)
Chapter 7: Combinational Circuits and Logic (slides) (handout)
Chapter 8: Sequential Circuits and Logic (slides) (handout)
Computer Architecture Overview
(slides)
Exam Review Slides
Exam 1 (slides) (handout)
Exam 2 (slides) (handout)
Homework Problems
Homework 1 due on 9/15/09 Homework 1 solutions
Homework 2 due on 9/24/09
Homework 3 due on 10/1/09
Homework 4 due on 10/20/09
Homework 5 due on 10/29/09
Homework 6 due on 11/5/09
Final Project
Project Description
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CSE463/CSE563: Digital Integrated Circuits Desgin and Architecture
