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High Resolution, Low Power Image Sensor

High resolution imaging has been closely associated with CCD technology. Improvements in technology and introduction of pinned photodiode have introduced CMOS voltage mode active pixel sensors as another contender in the imaging market. One of the main advantages of the CMOS imaging technology is the low power consumption compared to the CCD counterparts, which has secured a niche in the low power sensory devices, such as cell phones. High resolution imaging is closely related to the number of transistors and line interconnections per pixel. Traditional image sensors have been based on the three transistor active pixel sensor (APS) topology. In order to achieve high resolution imaging, various schemes have been explored where one or more of the three pixel transistors are shared within a neighborhood of pixels and effectively reducing the transistor count per pixel

We have designed a novel imaging sensor based on the linear current mode APS paradigm. The pixel switching transistor has been moved outside the pixel, allowing for an efficient realization of 2 transistors per pixel and effectively reducing the pixel pitch.  Furthermore, eliminating the switch transistor from the pixel has allowed for higher linearity between the output photo current and photodiode voltage. The improved linearity has yielded to low FPN figures.

A block diagram of the pixel schematic and the entire image array is presented in Figure 1. The photo pixel is composed of a photodiode, implemented as n-diffusion over p-substrate, and two transistors: a reset transistor M0 and a transimpedance amplifier M1. There are five line connections per pixel: power, ground, reset, drain and source line.

The image sensor is composed of 50 by 128 pixels and is fabricated in a standard 1P3M CMOS 0.5 micron process. Figure 2 shows sample images obtained from the image sensors. In Figure 8, image (a) presents the original image obtained directly from the image sensors without any noise suppression. In this image, large variations across the entire image, as well as column variations are observed and the features of the image are very difficult to be observed. Images (b) in both figures are obtained after the DDS operation. In this image, large variations across different rows are still visible due to the mismatches between row-parallel current conveyors. In the last two images, (c) and (d), the row calibration scheme and per pixel gain calibration scheme are applied respectively. The spatial variations in both of these images are minimized and the spatial noise improvements are clearly evident.

References:
[1] V. Gruev, Z. Yang and Van der Spiegel, "Low Power Current Mode Imager with 1.5 Transistors per Pixel," Proc. IEEE ISCAS, Seattle, USA, May 2008.
[2] V. Gruev, Z. Yang and J. Van der Spiegel, "Two Transistor Current Mode Active Pixel Sensor," Proc. IEEE ISCAS, New Orleans, USA, May 2007. (Upenn, IEEExplore)
[3] R. Philipp, D. Orr, V. Gruev, J. Van der Spiegel and R. Etienne-Cummings, "Linear Current-Mode Active-Pixels-Sensor," IEEE J. Solid-State Circuits, Vol. 42, No. 11, pp. 2482-2491, November 2007. (Upenn, IEEExplore)