*latch for metastability characterization

vdd  100 0 DC 1.8v
*                    V1 V2    TD               TR   TF   WID  PER
vck   clock 0 pulse(1.8  0    1ns              50ps 50ps 100n 200n)
vdata data 0 pulse(0   1.8    0.9455011n  50ps 50ps 100n 200n)

* this is a subcircuit or macro for a NAND gate
* 1 input (nfet closest to gnd), 2 input, 3 output, 4 vdd
.subckt nand1 1 2 3 4
*   D  G  S  B
mn1 20 1  0  0 nfet  l=0.18u w=1.44u
mn2 3  2  20 0 nfet  l=0.18u w=1.44u
mp1 3  1  4  4 pfet  l=0.18u w=1.44u
mp2 3  2  4  4 pfet  l=0.18u w=1.44u
c2  3  0  0.01pf
.ends nand1

* this is a subcircuit or macro for an inverter
* 1 input,  2 output,  3  vdd
.subckt inv 1 2 3
mn10 2 1 0 0 nfet  l=0.18u  w=0.72u
mp11 2 1 3 3   pfet  l=0.18u  w=0.72u
c1  3  0  0.005pf
.ends inv

* Clocked D Latch with 4 NANDS and and Inverter
* 
x1 clock data 5 100 nand1
x2 clock 3    4 100 nand1
x3 Qb    5    Q 100 nand1
x4 Q     4    Qb 100 nand1
x5 data  3    100 inv
c1 Q 0 0.002pf
c2 Qb 0 0.002pf
.model nfet nmos level=1 vto=0.4v kp=155e-6
.model pfet pmos level=1 vto=-0.4v kp=77.5e-6
.tran .001n 2n
.option post accurate=1
.print TRAN v(Qb) v(Q)
.end