CSE463 Digital Integrated Circuit Design and Architecture

Text: CMOS VLSI Design, Weste and Harris, 2005.

Introduction to VLSI circuit design and architecture including: FET transistor operation; design rules, fabrication, yield, and their interaction; gate design for noise margin, minimum delay and minimum area; system design for minimum delay and area (wires, not transistors are the primary limit to speed and area); clocking, clock generation, and clock distribution; power dissipation and power distribution; scaling to smaller dimensions, technology limits and fundamental limits; logic circuits and memory circuits; testing and testability; logical and electrical simulation.

Microprocessor, memory, and other integrated circuit capabilities continue to improve at an astounding rate. This course covers the reasons for this continuing improvement, how to take advantage of it for new circuits and systems, and limitations and problems that must be overcome to do so. The Figure below shows a chip photo of an ATM-switch integrated circuit containing hundreds of thousands of transistors that was designed by a team including graduates of EE463.