CSE463      Homepage     Fall 2004

Brief Overview of CSE463

Logistics

Preliminary Schedule

Grades

CSE463 CMOS IC Parameters, you need this for HW and tests

Homework (Note:  Assignment is not official until 168 hours before due date):


   Homework 0 (Due Sept 8, 2004, 11:00 AM)

   Intro Lecture, 2004-09-01

   Homework 1 (Due 2004-09-15,  4:00PM)  Due Date deferred to 2004-09-20

   Homework 2 (Due 2004-09-22, 4:00 PM)

   Homework 3 (Due 2004-10-04)     HSPICE file:  V-I-NFET.sp

   Homework 4 (Due 2004-10-11)

   Homework 5 (Due 2004-10-18)  Revised 2004-10-13

   Homework 6 (Due 2004-10-25)    fo4.sp     mosistsmc180.sp     opConditions.lib

   Homework 7 (Due 2004-11-08)

   Homework 8 (Due 2004-11-15)

   Homework 9 (Due 2004-11-22)

   Homework 10 (Due 2004-11-29)

   Mini-Project (Due 2004-12-20) Recommended to understand this assignment before the final exam

   Homework 11 (Due 2004-12-06)

   Quiz #0 Answer Sheet

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DLP TV http://www.tvauthority.com/dlp/dlp_tv.asp?dept=42

 

Weste-Harris Text Homepage

Text Errata:   See Text Homepage

FET Equations

IBM SA-12E 0.25u Process Data Book (SA12E Process is 0.25um, Warning: 13 Mbytes)

Summary of Spice         HSPICE Manual (warning: 16 Mbytes)       HSPICE Quick Ref Guide

180 nm process parameters

Notes on Metastability

Figures from Chapter 8 with notes

Spreadsheet for Problem 4-26 Solution

PLA Example, 8-bit counter

Links:

Metastability Patent: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=4,999,528.WKU.&OS=PN/4,999,528&RS=PN/4,999,528
Metastable Immune PLD: http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Problems/asp06/PDF/8175.pdf

http://www.research.ibm.com/people/r/restle/Animations/DAC01top.html  Clock distribution, Wire delay, etc
Dallas iButton web page (neat and tiny circuits, some with only two pins)
http://www.chips.ibm.com/ Microelectronics Design Magazine (IBM) and more
http://ge.ee.wustl.edu/HEP/ADK/HTMLdatasheets/ Data sheets for several CMOS cells
Mixed-Logic Notation, an example illustrating the advantage of mixed-logic.
Cute animations of CMOS gates and flop, you can toggle input values and see result.
http://micro.magnet.fsu.edu/primer/virtual/virtualzoo/index.html , Tiny pictures on integrated circuits

  http://www.dacafe.com/DACafe/NEWS/EDA_News/20010814_140445.html   blurb on hot-electron effects
http://public.itrs.net/Files/2000UpdateFinal/2kUdFinal.htm  projections on forthcoming IC technology

Last updated: 2004-09-22