The Packet Device provides a network packet transport interface for the Leon processor core operating in the FPX environment. Utilizing this device, software running on the Leon processor can send and receive network packets. The Packet Device sits on the Amba Peripheral Bus (APB) of the Leon processor. An interrupt to the processor is gernerated when packets arrice at the device. The lower layer portion of the Packet Device interfaces with the Layered Protocol Wrappers which provide packet framing and transmission services with external network devices.
The Packet Device is located at address 0x800000D0. The memory map
for this device is shown below:
| Address | Function |
0x800000D0
|
Initialization/Status
|
The Packet Device uses IRQ 13 to signal the presence of a network packet in the receive queue which is ready to be read.
Write the value zero to the Init/Status register. This will initialize the operation of the Packet Device, clearing all internal buffers and registers. Any packet currently being transmitted will be prematurely interrupted.
Checking the status of the Packet Device involves a write followed by a read to the Init/Status register.
| Value Written | Value Read |
1
|
Available TX buffer space (bytes)
|
The transmit packet operation involves two phases. During the first phase, the packet is transferred to the Packet Device. In the second phase, the transmit operation is initiated.
Start writing packet data to the TX/RX Data register, 32 bits at a time. The first word written should be the beginning of the IP header. Continue writing packet data to this register until all packet data has been written. If the length of the packet data is not divisible by 4, then the last data bytes should be aligned left (left-shifted) and written to the TX/RX Data register as the last data write operation. No padding or extra bytes should be written to the TX/RX Data register. They are not required by the Packet Device.
Once the complete packet has been written to the TX/RX Data register, the total packet length in bytes should be written to the TX/RX Length register. This write operation will initiate the transmit sequence.
The receive operation involves three phases. The first phase involves detection or notification that a packet is available. The second phase involves reading the packet length and the third phase corresponds to reading the packet data from the device.
The presence of a network packet can either be signaled by an interrupt or by a poll of the RX packets queued status register. The TX/RX Length register can also be polled to indicate the presence of a packet. Regardless of how the presence of a packet is detected, the subsequent operations are the same.
A read of the TX/RX Length register will indicate the length of the packet to be read. The value zero is returned when there is no packet available. If a non value is returned, the software should read (Length+3)/4 words from the TX/RX Data register.
If another packet arrices while the application is reading a packet from the Packet Device, an interrupt will not be generated. Upon reception of a receive interrupt, it is the responsibility of the software to read network packets from the receive engine until a zero length is returned from the TX/RX Length register.