Workshop on Network Processors & Applications - NP3

February 14-15, 2004
Madrid, Spain

Held in conjunction with
The 10th International Symposium on High-Performance Computer Architecture
February 14-18, 2004




As the performance and importance of digital communication networks have increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility and economy requirements, the networking industry has opted to build products around network processors. These processors are programmable yet application-specific; their designs are tailored to efficiently implement communications applications such as: routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS. The term network processor is used here in the most generic sense -- from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors.

Network processor design is an emerging field with numerous challenges and opportunities. The goal of this workshop is to provide a forum for engineers and scientists from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices.

Workshop Registration
Hotel Information
Travel Information

Advance Program

Saturday, February 14

1:25-1:30 Opening remarks
1:30-3:00 Session 1: Hardware 1

Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches
Patrick Crowley
Washington U

Efficient Packet Classification with Digest Caches
Francis Chang, Wu-chang Feng, Wu-chi Feng and Kang Li
OGI, U Georgia

Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express
Christian Sauer, Matthias Gries, Jose Ignacio Gomez and Kurt Keutzer
Infineon, UC-Berkeley, UCM
3:00-3:30 Break
3:30-4:30 Invited Talk
4:30-4:45 Short Break
4:45-6:00 Session 2: Industry Presentations

GEP2C02: A Network Processor for Real-time Content Switching
You-Sung Chang, Hun-Seung Oh, Ju-Hwan Yi, Jun-Hee Lee, Seung-Wang Lee, Jung-Bum Chun, Chong-Min Kyung
Paion Co.

Essential Network Search Engine Features for High Speed NPU-based Packet Searching
Michael Miller, Dave Cech and Scott Darnell

Taming the Network Processor: Challenges for Developing Reusable Network Software
Larry Huston

Using Network Processors to Improve Scalability and Availability of Routing/Signaling Protocols
Hormuzd Khosravi, Raj Yavatkar, Sanjay Bakshi, Manasi Deval, Rajeev Muralidhar, Suhail Ahmed

Sunday, February 15

8:25-8:30 Remarks
8:30-9:30 Session 3: Performance & Modelling 1

Pipeline Task Scheduling on Network Processors
Mark A. Franklin and Seema Datar
Washington U

A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs
Matthias Grünewald, Jörg-Christian Niemann, Mario Porrmann and Ulrich Rückert
U Paderborn
9:30-10:00 Break
10:00-11:00 Keynote Address

Network Processors and their Memory
Nick McKeown
Stanford U
11:00-11:15 Short Break
11:15-12:00 Session 4: Performance & Modelling 2

Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures
Ramaswamy Ramaswamy, Ning Weng and Tilman Wolf
U Massachusetts - Amherst

Analysis of Traffic Traces for Stateful Applications
Javier Verdú, Jorge García, Mario Nemirovsky and Mateo Valero
UPC, Tidal Networks
12:00-1:15 Lunch
1:15-2:45 Session 5: Hardware 2

A High-speed, Multi-threaded TCP Offload Engine for 10Gbps Ethernet
Yatin Hoskote, Sriram Vangal, Vasantha Erraguntla and Nitin Borkar

A Hardware Platform for Network Intrusion Detection and Prevention
Chris Clark, Wenke Lee, David Schimmel, Didier Contis, Mohamed Koné and Ashley Thomas
Georgia Tech

Packet Processing on a SIMD Stream Processor
Jathin S. Rai, Yu-Kuen Lai, and Gregory T. Byrd
NC State
2:45-3:15 Break
3:15-4:45 Session 6: Software

A Programming Environment for Packet-processing Systems:Design Considerations
Harrick Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson, Roy Ju, Aaron Kunze and Ruiqi Lian
UT-Austin, Intel, Chinese Academy of Sciences

RNOS: A Middleware Platform for Low Cost Packet Processing Devices
Jonas Greutert and Lothar Thiele
Netmodule, ETH Zürich

On the Feasibility of Using Network Processors for DNA Queries
Herbert Bos and Kaiming Huang
Vrije U, U Leiden
4:45-5:00 Short Break
5:00-6:00 Industry Panel

Program Committee

Alan Berenbaum, Agere
Brad Calder, UCSD
Andrew Campbell, Columbia University
Patrick Crowley, Washington University in St. Louis
Jordi Domingo, UPC (Spain)
Mark Franklin, Washington University in St. Louis
Jorge Garcia, UPC (Spain)
Haldun Hadimioglu, Polytechnic University
Marco Heddes, Transwitch Corporation
Manolis Katevenis, FORTH and University of Crete (Greece)
Bill Mangione-Smith, UCLA
Kenneth Mackenzie, Reserviour Labs
John Marshall, Cisco
Daniel Mlynek, EPFL (Switzerland)
Peter Z. Onufryk, IDT
Lothar Thiele, ETH Zürich (Switzerland)
Jon Turner, Washington University in St. Louis
Mateo Valero, UPC (Spain)
Tilman Wolf, University of Massachusetts
Raj Yavatkar, Intel


Patrick Crowley, Washington University in St. Louis (
Mark Franklin, Washington University in St. Louis (
Haldun Hadimioglu, Polytechnic University (
Peter Z. Onufryk, IDT (

NP2 at HPCA 9 (2003) (webpage)

Selected papers from NP2 and additional industry contributions appear in Network Processor Design : Issues and Practices Volume II (Morgan Kaufmann Publishers, September 2003).

NP1 at HPCA 8 (2002) (webpage)

Selected papers from NP1 and additional industry contributions appear in Network Processor Design : Issues and Practices Volume I (Morgan Kaufmann Publishers, September 2002).