Monday, Dec 4, 2006
Day 1
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7:00-8:40 AM
Continental Breakfast & Registration
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8:40 - 9 AM
Opening Remarks
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9 - 10 AM
Keynote 1- Multi-Core Processors for Networking and Communication Equipment
Talk Slides
Muhammad Raghib Hussain
VP and Chief Technology Officer at Cavium Networks
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10 - 10:20 AM
Break
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10:20AM - 12PM
Session
1: Switches & Routers
Session Chair: Will Eatherton
Design of a Web Switch in a Reconfigurable Platform (slides)
Christoforos Kachris (Delft University of Technology, NL); Stamatis
Vassiliadis (TU Delft, NL)
Symerton - Using Virtualization to Accelerate Packet Processing (slides)
Aaron Kunze (Intel Corp, US); Stephen Goglin (Intel Corporation, US);
Erik Johnson (Intel Corp, US)
Towards an Efficient Switch Architecture for High-Radix Switches (slides)
Gaspar Mora (Universidad Politecnica de Valencia, ES); Jose Flich
(Universidad Politecnica de Valencia, ES); Jose Duato (Universidad
Politecnica de Valencia, ES); Elvira Baydal (Technical University of
Valencia, ES); Pedro Lopez (Universidad Politécnica de
Valencia, ES); Olav Lysne (Simula Research Laboratory, NO)
A practical fast parallel routing architecture for Clos networks
Si-Qing Zheng (University of Texas at Dallas, US)
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12 - 1 PM
LUNCH
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1 - 2:15 PM
Session
2: Lookups & Classification
Session Chair: Srinivasan Venkatachary
CAMP: Fast and Efficient IP Lookup Architecture (slides)
Sailesh Kumar (Washington University, US); Michela Becchi (Washington
University in St. Louis, US); Patrick Crowley (Washington University in
St. Louis, US); Jonathan Turner (Washington University in St. Louis,
US)
Fast Packet Classification Using Bloom Filters
Sarang Dharmapurikar (Washington University, US); Haoyu Song
(Washington University in St. Louis, US); Jonathan Turner (Washington
University in St. Louis, US); John Lockwood (Washington University in
St. Louis, US)
Sequence-Preserving Adaptive Load Balancers (Note: This talk has been moved from its original session for scheduling purposes.)
Lukas Kencl (Intel Research, UK); Weiguang Shi (University of Alberta,
CA)
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2:15 - 2:35 PM
Break
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2:35 - 3:50 PM
Session
3: Content Inspection
Session Chair: Bapi Vinnakota
Advanced Algorithms for Fast and Scalable Deep Packet Inspection (slides)
Sailesh Kumar (Washington University, US); Jonathan Turner (Washington
University in St. Louis, US); John Williams (Cisco Systems, US)
Fast and Memory-Efficient Regular Expression Matching for Deep Packet
Inspection (slides)
Fang Yu (University of California, Berkeley, US); Zhifeng Chen (Google
Inc, US); Yanlei Diao (University of Massachusetts Amhers, US); T. v.
Lakshman (Bell Labs, Lucent Technologies, US); Randy H. Katz
(University of California at Berkeley, US)
Efficient Memory Utilization on Network Processors for Deep Packet
Inspection (slides)
Piti Piyachon (University of Massachusetts Lowell, US); Yan Luo
(University of Massachusetts Lowell, US)
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Tuesday, Dec 5, 2006
Day Two
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7 - 9AM
Continental Breakfast
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9 - 10 AM
Keynote 2- Router/Switch Control Plane Software Challenges
Talk Slides
Michael Beesley
Director and CTO for the Midrange Router Business Unit at Cisco Systems
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10 - 10:20 AM
Break
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10:20 - 12 PM
Session
4: Packet Processing Architectures
Session Chair: Patrick Crowley
A Proposed Architecture for the GENI Backbone Platform (slides)
Jonathan Turner (Washington University in St. Louis, US)
An Effective Network Processor Design Framework - Using
Multi-Objective Evolutionary Algorithms and Object Oriented
Techniques to Optimise the Intel IXP1200 Network Processor (slides)
Liam Noonan (University Of Limerick, IE); Colin Flanagan (University of
Limerick, IE)
A Methodology for Evaluating Runtime Support in Network Processors (slides)
Xin Huang (University of Massachusetts, Amherst, US); Tilman Wolf
(University of Massachusetts, Amherst, US)
High-Throughput Sketch Update on a Low-Power Stream Processor (slides)
Yukuen Lai (North Carolina State University, US); Gregory Byrd (North
Carolina State University, US)
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12 - 1 PM
LUNCH
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1 - 1:50 PM
Session
5: Scheduling
Session Chair: Bob Olson
Localized Asynchronous Packet Scheduling for Buffered Crossbar Switches (slides)
Deng Pan (State University of New York at Stony Brook, US); Yuanyuan
Yang (State University of New York at Stony Brook, US)
Compressed Tuple Space Packet Classification (slides) (Note: This talk has been moved from its original session for scheduling purposes.)
Haoyu Song (Washington University in St. Louis, US); Jonathan Turner
(Washington University in St. Louis, US); Sarang Dharmapurikar
(Washington University, US)
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1:50 - 2:10 PM
Break
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2:10 - 3:25 PM
Session
6: End-to-end Security
Session Chair: Jon Turner
Scalable Network-Based Buffer Overflow Attack Detection (slides)
Fu-hau Hsu (National Central
University, TW); Fanglu Guo (State University of New York at Stony
Brook, US); Tzi-Cker Chiueh (State University of New York at Stony
Brook, US)
WormTerminator: An Effective Containment of Unknown Fast Spreading Worms (slides)
Songqing Chen (George Mason
University, US); Xinyuan Wang (George Mason University, US); Lei Liu
(George Mason University, US); Xinwen Zhang (George Mason University,
US); Zhao Zhang (Iowa State University, US)
Packet Pre-filtering for Network Intrusion Detection (slides)
Ioannis Sourdis (Deflt
University of Technology, NL); Vasilis Dimopoulos (Technical University
of Crete, GR); Dionisios Pnevmatikatos (Technical University of Crete,
GR); Stamatis Vassiliadis (TU Delft, NL)
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3:25 - 3:35 PM
CLOSING REMARKS/ADJOURN
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